1. Field of the Invention
This invention generally relates to a semiconductor integrated circuit device and a method of manufacturing the same. More particularly, it relates to a technology effectively applicable to a semiconductor integrated circuit device comprising a DRAM (dynamic random access memory).
2. Related Art
DRAMs are typical large capacity semiconductor memories known to date. Recently, as DRAMs are made to have an ever-increasing storage capacity, the area exclusively occupied by the memory cells of a DRAM has to be reduced in order to enhance the degree of integration of the memory cells.
However, the storage capacity of the information storing capacitive elements (hereinafter referred to simply as capacitors) of the memory cells of a DRAM has to be held to a constant level regardless of the DRAM generation by taking the operational margin and software errors as well as other factors of the DRAM into consideration.
Thus, research and development efforts have been paid to improve the structure of capacitors so that a required storage capacity may be secured within a limited area provided exclusively for the capacitors of a DRAM. As a result of such efforts, cubic capacitor structures have been developed by arranging a plate electrode on a lower electrode having a crown-like three-dimensional profile and typically made of polysilicon with a capacitive insulation film interposed between the plate electrode and the lower electrode. Such structures are currently popularly used.
In capacitors having a cubic profile, or cubic capacitors, the capacitor electrode is normally arranged as an upper layer relative to the memory cell selector MISFET (metal insulator semiconductor field effect transistor: hereinafter referred to simply as selector MISFET) so that a large storage capacity may be secured within a relatively small area.
Japanese Patent Application Laid-Open No. 7-122654 describes a cubic capacitor structure known as capacitor over bit line (hereinafter referred to as COB) structure where the capacitor is arranged above the bit line.
In a DRAM having a COB structure, a selector MISFET and a MISFET for the peripheral circuit are formed on a semiconductor substrate and a bit line for writing and reading data and a first wiring layer of the peripheral circuit are formed above the selector MISFET with an interlayer insulation film interposed therebetween. Subsequently, a capacitor is formed by sequentially laying a storage electrode (lower electrode), a capacitive insulation film and a plate electrode (upper electrode) to produce a multilayer structure. The storage electrode of the capacitor is made of polycrystal silicon doped with an n-type impurity substance (phosphor) and connected to one of the semiconductor regions (the source or drain region) of the selector MISFET, which is of the n-channel type. The plate electrode is arranged as an electrode commonly used for a plurality of memory cells and held to a predetermined constant potential.
The bit line is connected to one of the semiconductor regions (source/drain regions) of the selector MISFET through a contact hole cut through the insulation film that covers the selector MISFET. This connection is realized by way of a polycrystal silicon plug formed in the contact hole. The other semiconductor region of the selector MISFET is connected to the capacitor. The bit line is typically made of a low resistance metal material in order to improve the speed of the data writing/reading operation.
In a DRAM having a configuration as described above, tungsten (W) film is used for the bit line or the first wiring layer of the peripheral circuit. The use of tungsten that is more resistive against electro-migration than aluminum (Al) for the bit line or the first wiring layer of the peripheral circuit provides an effective means for securing a prolonged service life for the wires of the DRAM.
However, more often than not, the metal material of the wires and the silicon of the substrate chemically react each other to produce a silicide layer in areas where the wires and the substrate contact each other. The silicide (tungsten silicide) layer formed by the chemical reaction of the tungsten film and the silicon substrate can generate significant stress in the substrate. Therefore, when the bit line or the first wiring layer of the peripheral circuit is made of tungsten film, a metal film has to be formed under the tungsten film so that there may be given rise to a silicide layer that is subjected to little stress by the chemical reaction of the metal film and the silicon substrate.
The above cited patent document describes the use of titanium (Ti) film as metal film that gives rise to a silicide layer with little stress. Titanium film adheres well to insulation film and the titanium silicide (TiSi.sub.x, x.ltoreq.2) layer it produces as it reacts with the silicon substrate generates little stress in the substrate. Thus, titanium silicide is a material that can advantageously be used for the metal layer to be formed under the tungsten layer.
Additionally, a titanium silicide film formed on the interface between the semiconductor regions (source/drain regions) of the MISFET of the peripheral circuit and the first wiring layer operates as effective means for reducing the contact resistance of the wires of the device.
On the other hand, there is a problem of the chemical reaction between WF6 of the source gas and silicon (Si) that arises when forming a tungsten film by means of a CVD technique. Additionally, the tungsten film can react with silicon in a subsequent heat treatment process if they are held in direct contact with each other. Therefore, for forming a tungsten film on a titanium film by deposition, it is necessary to provide a barrier layer between the two films that adheres well to them in order to prevent any direct contact of WF6 and silicon or tungsten and silicon. The above cited patent document refers to the use of titanium nitride film (TiN) as barrier layer.
DRAMs generally comprises a memory cell array region, a direct peripheral circuit region and an indirect peripheral circuit region. The memory cell array region is a region where selector MISFETs and capacitors are formed, whereas sense amplifiers are formed in the direct peripheral circuit region to detect the presence or absence of a stored electric charge in each capacitor as recorded information. The indirect peripheral circuit region is formed around the direct peripheral circuit region. The word lines and the bit lines in the memory cell array region of a DRAM are processed with minimum processing dimensions in order to provide the DRAM with a maximal degree of integration. Then, in the direct peripheral circuit region, the MISFETs are processed with minimum processing dimensions and arranged at a pitch that is in line with that of arranging the word lines and the bit lines that have been processed with minimum processing dimensions. Furthermore, the gate electrodes and the contact holes for contacting the source/drain regions are generally also processed with minimum processing dimensions. On the other hand, the indirect peripheral circuit region is subjected to less rigorous requirements in terms of device layout and it is less influential in determining the total area of the chip so that the contact holes for contacting the source/drain regions of the MISFETs can be made to have a large bore in order to realize a reliable contact.
However, as the degree of integration is raised for DRAMs, the area in a DRAM exclusively spared for the capacitors is reduced to consequently reduce their storage capacity. Then, it is necessary to improve the sensitivity of the sense amplifiers and provide measures to reduce the capacity of the bit lines so that the presence or absence of a stored electric charge may be reliably detected in each of the capacitors that have only a small capacity. In order to reduce the capacity of the bit lines, it is necessary to reduce the width of the bit lines and increase the gap separating adjacent bit lines or reduce the film thickness of the bit lines so that adjacently located bit lines may face each other with a minimal surface area.
Additionally, it is also necessary to reduce the area occupied by the memory cell array region who is the largest occupier in the DRAM and minimize the surface area of the chip if the degree of integration is to be enhanced for the DRAM. The area occupied by the memory cell array region can be reduced only by optimally selecting the profiles and the positions of the contact holes for contacting the active regions of the selector MISFETs of the memory cells, the word lines, the bit lines and the capacitors as well as other members. Note that the above listed members should not be made to show a complicated profile as a result of such optimization. More specifically, in the memory cell array region, the members are processed for patterning by exploring the technological limits of photolithography because they are processed with minimum processing dimensions. If the members have a complicated profile, defective patterns can be produced by the patterning operation due to interference of rays of light used for exposure as such interference can occur among adjacently located members. Thus, the members are required to show a profile that is as simple as possible. In the case of word lines and bit lines, a linear profile will be the best choice.
However, with bit lines having a linear profile and a minimal width, it will no longer be possible to completely cover the contact area of each bit line and the polycrystal silicon plug formed on the source/drain regions of a corresponding selector MISFET, which is a bit line contact hole, so that consequently and inevitably the bit line contact hole will remain open relative to the bit line. Then, the bit line contact hole will become etched during the operation of etching the bit line.
When bit lines are processed in such an open structure, the polycrystal silicon plug underlying the bit lines can be dug to produce undulations on the underlayer, which adversely affect the subsequent photolithography and etching steps to degrade the overall processing accuracy.
As described earlier, a titanium silicide film is formed between each bit line and the corresponding polycrystal silicon plug to reduce the contact resistance. However, when a bit line is etched in an open structure, the titanium silicide film that is apt to be etched can also be etched transversally to produce a cavity between the bit line and the polycrystal silicon plug. Then, such a cavity can hinder the communication between the bit line and the polycrystal silicon plug to consequently degrade the performance of the DRAM.
On the other hand, as also described earlier, the bit lines and the first wiring layer are formed as a common layer and a titanium silicide film is formed at the contacts of the first wiring layer and the semiconductor substrate. The titanium silicide film has a thermal resistance that is not sufficient to withstand the heat treatment process to be conducted after the formation of the bit lines and the first wiring layer so that a problem of an increased leak current can arise at their contacts. Particularly, the inventors of the present invention have noticed that the thermal resistance is particularly poor when the contact holes have a bore that is different between the direct peripheral circuit region and the indirect peripheral circuit region. Then, such a rise in the leak current, or a fall in the withstand voltage at the contacts, will become particularly remarkable when unreacted titanium is left on the bottom of any of the contact holes.
Thus, it is an object of the present invention to provide a technology for effectively preventing undulations from being produced in the polycrystal silicon plugs in the bit line contact holes to eliminate any possible adverse effect of such undulations on the subsequent photolithography and etching steps and improve the yield of these steps.
Another object of the present invention is to provide a technology for preventing the phenomenon that the silicide film at the contacts of the bit lines and the polycrystal silicon plugs is etched transversally from taking place in order to secure the communication between each bit line and the corresponding polycrystal silicon plug and consequently improve the yield and the reliability of manufacturing semiconductor integrated circuit devices.
Still another object of the present invention is to provide a technology for reducing the capacity of each bit line and hence the storage capacity of a DRAM required to store a given amount of information so that the operating speed of the DRAM may be improved.
A further object of the present invention is to provide a technology for improving the thermal resistance of the contacts between the first wiring layer and the semiconductor substrate and suppressing the leak current at the contacts that can appear in subsequent steps involving the use of heat particularly when the bit lines of the DRAM and the first wiring layer of the peripheral circuit region are formed in a common layer so that consequently the yield and the reliability of manufacturing semiconductor integrated circuit devices may be improved.
These and other objects and the novel features of the present invention will become more apparent by reading the following description made in conjunction with the accompanying drawings.